1. Technical Field
The present invention relates generally to electronic circuits and in particular to phase locked loop (PLL) circuits. Still more particularly, the present invention relates to calibration of the PLL circuits.
2. Description of the Related Art
Voltage controlled oscillator (VCO) calibration algorithm is utilized in the 6 Gbps harmonic oscillator for high speed serial (HSS) links. However, in electronic circuits and particularly phase locked loop (PLL) circuits, VCO calibration causes frequency overshoot. Most conventional approaches to VCO calibration do not adjust for Overshoot, which is a condition that frequently occurs during the calibration.
FIGS. 1, 3, 5, and 7 are example graphs illustrating the application of the prior art calibration algorithm to a PLL circuit. Each graph tracks the voltage (+ or − from a 0 voltage, central reference point) along the bottom X axis and the frequency band (relative to the voltage) along the right most vertical edge (Y axis). Six points of reference are shown within the graph of FIG. 1, one associated to frequency zero (F0), two associated with frequency one (F1), and three associated with frequency two (F2). Three of the points of reference are indicated with the selected frequency band assigned/selected.
In conventional designs of circuits that utilize VCO calibration, frequency overshoot caused by VCO calibration is tracked by divider circuitry to prevent erroneous lock conditions in the circuit. These conventional circuits require the divider be over-designed (i.e., built to require more power and area) in order to track the VCO. However, given the ever-present desire for smaller and lower power consuming circuits, the use of such over-designed dividers provided for correct VCO calibration is a less-than desirable fix to the problem of overshoot.